(1) Field of the Invention
The invention relates to memory devices, and, more particularly, to a memory device based on vertical FET devices in an integrated circuit device.
(2) Description of the Prior Art
Memory devices are very important in the art of digital electronics. Memory devices are used to store software programs and processed data. Write capable memory, such as RAM, is particularly important for storing data. Static RAM, or SRAM, is of particular importance in the present invention. In a SRAM device, data written to a memory cell can be stored indefinitely as long as power is supplied to the cell. Further, the stored data can be changed by rewriting the cell. However, unlike a dynamic RAM, or DRAM, the data value does not have to be periodically refreshed.
Referring now to FIG. 1, a typical SRAM cell 10 is shown in schematic form. The SRAM cell 10 comprises six MOS transistors and is therefore called a 6T cell. In particular, the cell comprises NMOS transistors N134 and N242, PMOS transistors P130 and P238, and NMOS transistors S146 and S250. Transistor pairs N134 and P130 form a first inverter and N242 and P238 form a second inverter. Note that the input of the first inverter 30 and 34 is coupled to the output of the second inverter 38 and 42. Similarly, the input of the second inverter 38 and 42 is coupled to the output of the first inverter 30 and 34. In this arrangement, a digital latch is formed. The digital latch 30, 34, 38, and 42, has two key nodes A 35 and B 43. The digital latch is electrically able to maintain either of two states. In one state, A is high and B is low. In the other state, A is low and B is high.
Transistors S146 and S250 are used to control access to the digital latch 30, 34, 38, and 42. The access transistors 46 and 50 are controlled by a common signal, called a word line (WL) 20. When WL is asserted, the access transistors 46 and 50 are ON. In this state, the bit line (BL) 22 is coupled to node A 35, and the bit line bar (BLB) is coupled to node B. If the WL assertion is due to a READ of the cell 10, then the BL 22 and BLB 26 signal lines will be coupled to a high impedance input stage of a bit line amplifier, not shown. This amplifier will be used to read the voltage state (high or low) of the BL 22 and BLB 26 signals to thereby determine the stored state of the cell 10. If the WL 20 assertion is due to a WRITE operation, then the BL 22 and BLB 26 signals will be driven to opposite voltages (VCC and VSS) by the writing circuit. This will force the digital latch nodes A 35 and B 43 to the proper write state. When WL 20 is de-asserted, the access transistors S146 and S250 are turned OFF, and the write state is held in the digital latch.
The SRAM cell 10 has several advantages. First, the standby current of the cell is quite low due the complimentary MOS (CMOS) devices. A current path from VCC 14 to VSS 18 exists only during switching. Second, a large number of cells 10 can be designed into a memory array such that a large amount of data can be stored. Any cell in the array can be accessed by an addressing scheme as is well known in the art. In should be noted, however, that the SRAM cell 10 requires six transistors to store a single bit of data.
Referring now to FIG. 2, a top layout view of the SRAM cell 10 is shown. Several integrated circuit layers are shown in this simplified layout. In particular, n-type active areas 64 and p-type active areas 60 are shown. A polysilicon level 68, a metal level 72, and a contact level 76 are also shown. As is well known in the art of MOS integrated circuit fabrication, MOS transistors are formed where the polysilicon level 68 crosses the active areas 60 or 64. In particular, the PMOS transistors P130 and P238 are formed where the polysilicon level 68 crosses the p-type active area 60. The NMOS transistors N134, N242, S146, and S250, are formed where the polysilicon level 68 crosses the n-type active area 64. Contact openings 76 are formed in a conformal dielectric layer. The metal level 72 connects elements though the contact openings 76.
Several facts should be noted with regard to the typical CMOS SRAM cell shown. First, the MOS devices are formed on the surface of the integrated circuit wafer. It is found in the art that most integration effort is devoted to reducing the sizes of surface features (line widths and spaces, opening widths and spaces). By reducing these dimensions, SRAM cell density can be increased. Second, reducing the width and spacing of the surface features frequently creates new problems. For example, as the spacing between adjacent lines is reduced, it typically becomes more difficult to reliably etch the lines. Finally, the typical SRAM cell 10 takes no advantage of the considerable wafer volume that underlies the cell area. Much of the silicon area is wasted by isolation areas that are formed between the active areas 60 and 64.
Several prior art inventions relate to SRAM cells and vertical FET devices. U.S. Pat. No. 6,117,722 to Wuu et al describes a SRAM device and method of manufacture using dual fill STI. U.S. Pat. No. 6,313,490 B1 to Noble teaches a SRAM memory cell based on a base-current mechanism. Vertical FET devices are used. U.S. Pat. No. 6,297,531 B2 to Armacost et al discloses a method to form vertical FET devices using epitaxial layers. A 6T SRAM cell is described in the technology. U.S. Pat. No. 6,137,129 to Bertin et al describes a method to form a latch comprising a pair of complimentary FET devices having directly coupled gates. The gate of the NFET device is coupled to the drain of the PFET device. The gate of the PFET device is coupled to the drain of the NFET device. The devices are formed using epitaxial deposition and share a common gate dielectric. A SRAM cell is disclosed in the technology. U.S. Pat. No. 4,890,144 to Teng et al shows a vertical FET formed in a trench. A SRAM cell is disclosed.